下列Verilog HDL程序所描述电路功能是（ ）module ShiftReg (Q,Din,CP,CLR_); input Din; //Serial Data inputs input CP, CLR_; //Clock and Reset output reg [3:0] Q; //Register output always @ (posedge CP or negedge CLR_) if (!CLR_) Q <= 4'b0000; else begin //Shift right Q[0] <= Din; Q[3:1] <= Q[2:0]; endendmodule
![下列Verilog HDL程序所描述电路功能是（ ）<strong>module</strong> ShiftReg (Q,Din,CP,CLR_); <strong>input</strong> Din; //Serial Data inputs <strong>input</strong> CP, CLR_; //Clock and Reset <strong>output</strong> <strong>reg</strong> [3:0] Q; //Register output <strong>always</strong> <strong>@</strong> (<strong>posedge</strong> CP <strong>or</strong> <strong>negedge</strong> CLR_) <strong>if</strong> (!CLR_) Q <= 4'b0000; <strong>else begin </strong>//Shift right Q[0] <= Din; Q[3:1] <= Q[2:0]; <strong>end</strong><strong>endmodule</strong>](https://www.catpuzi.com/wp-content/themes/Git-alpha/timthumb.php?src=https://www.catpuzi.com/wp-content/themes/Git-alpha/assets/img/pic/9.jpg&h=160&w=260&q=90&zc=1&ct=1)
